1. Field of the Invention
The present invention relates generally to digital receivers for spread spectrum signals such as those used in Global Positioning System (GPS), and more particularly to a frequency discriminator and data demodulation techniques used in the carrier frequency lock loop (FLL) of digital code division multiple access (CDMA) spread spectrum receivers.
2. Description of the Prior Art
Global Positioning System (GPS) is a satellite-based radio navigation system. Each GPS satellite, also called space vehicle (SV), continuously transmits time-tagged spread-spectrum signals on two L-band carrier frequencies. Carriers are used for modulation of GPS signals, to be transmitted. “Carrier” and “carrier signal” are used interchangeably herein. Briefly, carrier is a sine/cosine wave characterized by its frequency. “Carriers” or “carrier signals”, at a carrier frequency, as often referred to herein, are modulated by binary bits or code. Upon reception of a modulated signal, the carrier must be removed or the signal need be demodulated using a receiver-generated carrier at the same frequency as that of the received signal's carrier frequency in order to recover bits or code.
In GPS satellite-based radio navigation systems, each carrier is modulated by at least one of two pseudorandom noise (PRN) codes unique to the satellite. The L1 carrier at 1575.42 MHz is modulated by both the precise (P) code and the coarse/acquisition (C/A) code. The L2 carrier at 1227.60 MHz is modulated by the P code only. The encrypted P code is available only to military and other authorized users, while the C/A code is public to all commercial and civilian users.
The GPS radio-frequency (RF) signals of all SVs in view, captured by a GPS receiver antenna, are amplified and down-converted to an intermediate frequency (IF) that is further digitalized by an analog-to-digital (A/D) converter, as show in FIG. 1. A digital receiver channel consists mainly of a carrier tracking loop and a code tracking loop, as shown in FIG. 2.
FIG. 1 is a block diagram illustrating, generally, the components of a typical GPS receiver 10. The receiver 10 is shown to include a GPS antenna 12 coupled to a pre-amplifier block 14, which is shown coupled to a down-converter block 16, which is, in turn, shown coupled to a IF filter block 18. The block 18 is shown coupled to an A/D converter block 20, which is shown coupled to an N number of digital receiver channels 22 for providing measurement input to a navigation processing (or position-velocity-time estimation) block 24. The blocks appearing before or to the left of the N number of digital receiver channels 22 process information that is in analog form, whereas, the blocks appearing to the right of or after the block 20 process signals that are in digital form.
The GPS antenna 12 first captures GPS RF signals of all satellites that are in view. The captured RF signals are then amplified, by the pre-amplifier block 14 and down-converted, by the down-converter block 16 and provided to the IF filter block 18, the output of which is provided to the A/D converter block 20 for digitization thereof and provided to each of N number of digital receiver channels 22. One receiver channel tends to track signals of one satellite, measures code and carrier phases, and demodulates navigation data bits. When there are four or more satellite measurements available, the receiver can have a position, velocity and time (PVT) information, which is processed by the block 24.
FIG. 2 is a block diagram illustrating the carrier and code tracking loops in one of the N number of digital receiver channels 22 of FIG. 1. In FIG. 2, a digital receiver channel 26 is shown to include a carrier removal block 28 coupled to a code wipeoff block 30, which is shown coupled to an integrate and dump block 32, which is shown coupled to a code loop discriminator block 34 and a carrier loop discriminator block 40. The block 34 is shown coupled to a code loop filter block 36, which is shown to provide input to the code numerically-controlled oscillator (NCO) block 38. The block 38 provides properly-delayed PRN code to the block 30—“properly” refers to the receiver-generated code and carrier being properly delayed in order to match the received code and carrier—. The block 40 is shown coupled to the carrier loop filter block 42, which is shown coupled to the code NCO block 38 and to the carrier NCO block 44. The block 44 is shown to provide carrier signals having a proper phase delay or a delay at a proper frequency, to the block 28. The blocks 28, 30, 32, 40, 42 and 44 comprise the carrier tracking loop, as they cause tracking of the received signals' carrier phase or frequency and the blocks 28, 30, 32, 34, 36 and 38 comprise the code tracking loop for tracking of the received signals' PRN code phase. The block 28 receives, as input, a digital IF signal generated by the block 20 of FIG. 1.
The digital receiver channel 26 accomplishes signal tracking with a carrier tracking loop and a code tracking loop. The carrier tracking loop removes the carrier (plus carrier Doppler due to line-of-sight relative motion between the receiver and the satellite) from the digital IF signal and produces in-phase (I) and quadrature-phase (Q) sampled data for use by the block 30. The carrier tracking loop is designed to synchronize the phase or frequency of the local NCO with that of the received carrier signal.
The code tracking loop is often implemented as a delay lock loop (DLL). The DLL correlates the I and Q signals normally with early, prompt, and late replica codes to maintain PRN code lock, resulting in IE, QE, IP, QP, IL and QL samples. The GPS 50-Hz navigation message data modulation remains after the carrier removal and code wipeoff. The block 32 provides signal integration, resulting in filtered IES, QES, IPS, QPS, ILS and QLS samples. The integration time defines the pre-detection filter bandwidth. Based on the locked code phase, the signal transit time from the satellite to the receiver and therefore the distance (called pseudorange) between them can be measured. The receiver can compute its PVT if there are four or more pseudorange measurements available.
The carrier tracking loop can be implemented either as a phase lock loop (PLL) or as a frequency lock loop (FLL), based on its discriminator function. It can also be used to demodulate navigation data bits. A Costas PLL offers accurate carrier phase measurements and easy data demodulation mechanism, but the PLL is sensitive to dynamics stress potentially causing it to even lose tracking of a strong signal. On the other hand, the FLL relies on frequency measurements; it is more robust for tolerating dynamic stress. Unfortunately, data demodulation is more complicated in a FLL than in a PLL.
FIG. 3 is a phasor diagram illustrating a typical method of estimating the frequency error in a FLL. Phasor Aa at time ta, which is the vector sum of Ia and Qa components, has a carrier phase angle of Φa=tan−1(Qa/Ia). If an adjacent pair of samples Ib and Qb is sampled within the same data bit interval as Ia and Qa, then their phase difference Φb−Φa, divided by their time difference tb−ta, is an estimate of the frequency error. Assuming that the pre-detection coherent integration time (PDI) in block 32 is TPDI, then the detected frequency error is equal to
                                                                        tan                                  -                  1                                            ⁡                              (                                                      Q                    b                                    /                                      I                    b                                                  )                                      -                                          tan                                  -                  1                                            ⁡                              (                                                      Q                    a                                    /                                      I                    a                                                  )                                                          2            ⁢            π            ⁢                                                  ⁢                          T              PDI                                      ⁢                                  ⁢        in        ⁢                                  ⁢                  Hz          .                                    Eq        .                                  ⁢                  (          1          )                    Theoretically, the FLL discriminator, of the block 40 of FIG. 2, can detect a maximum frequency error of
  +      /          -                        1                      2            ⁢                          T              PDI                                      .            For example, if TPDI equals 10 ms, a maximum +/−50 Hz frequency error can be detected. This frequency error detection range is directly related to the pull-in range of a carrier tracking loop. The larger the detection range, the more frequency error is tolerable for a receiver to handoff from acquisition to tracking. The large frequency error tolerance also makes an FLL more appealing than a PLL when a receiver uses a low-cost oscillator and frequently experiences user dynamics. However, phase angle difference quantities are usually noisier than the phase angle measurements themselves, which also result in noisy frequency error estimate. This is one of the problems associated with prior art techniques of estimating the frequency error accuracy.
In FIG. 3, if the NCO generated frequency matches the incoming signal carrier, then the frequency error will be zero. Since the two sampling times ta and tb are within the same bit interval, this frequency error estimation method is insensitive to bit transitions; however, the variance of phase difference (Φb−Φa) generally is twice as the variance of the phase Φa or Φb, which leads to a noisy frequency error estimate.
FIG. 4 is a graph illustrating a binary phase shift keying (BPSK) modulation, which is used as the GPS navigation data modulation method. In BPSK, the carrier phase has a 180-degree (or π) phase shift when a data bit transition occurs. For example, at times 20 ms and 60 ms in FIG. 4, the data bit transitions are from 0 to 1 and from 1 to 0, respectively. Accordingly, the carrier phase has a π phase shift at these two bit transitions. The π carrier phase shifts, caused by unknown bit transitions, make data modulation difficult in an FLL.
Accordingly, there is a need for improving data demodulation in FLL utilized in digital CDMA spread spectrum receivers including GPS receivers. Furthermore, there is a need to improve the frequency error estimate accuracy in order to more accurately adjust the frequency of the receiver's generated carrier signal to match that of the received carrier signal and to continue to adjust to compensate for frequency shifts due to Doppler effects resulting from a moving receiver and/or satellite.